A phase locked loop (PLL) is a negative feedback circuit that synchronizes the edges of a local clock with the edges of a reference clock. A PLL aligns the phases and frequencies of the clocks and helps to eliminate skew and jitter. A typical supply-regulated PLL includes a charge pump that translates control signals into an output voltage that controls a voltage-controlled oscillator (VCO) which outputs the local clock. The “up” and “down” control signals input into the charge pump denote when the local clock lags or leads the reference clock, respectively. If an “up” signal is received, the charge pump outputs a higher voltage that causes the VCO to output an increased frequency, and conversely, if a “down” signal is received, the charge pump outputs a lower voltage that causes the VCO to output a decreased frequency.
The charge pump relies on the generation of an internal reference current to create the output voltage that is sent to the VCO. Two current sources, a source current and a sink current, may be referenced and mirrored to the reference current, which is preferably constant over all operating conditions and manufacturing process corners, in order to improve the stability and open-loop phase margin of the PLL. The two current sources may source or sink current to vary the output voltage, based on the “up” and “down” signals. Reducing variability in the reference current directly translates into improved stability and phase margin of the PLL. Existing reference current generators may be strongly influenced by variations in the supply voltage, temperature, and/or process corner, leading to decreased stability and phase margin of the PLL. The reference current could also be generated using a circuit based on a bandgap voltage reference, but such circuits may consume significant power and require a large die area.